1. Field of the Invention
The present invention relates to a circuit, and more particularly to a circuit for adjusting a signal length which can be applied to an electronic storage device.
2. Description of the Related Art
For many memory devices, an address transition detection (ATD) signal generation circuit has been used to generate ATD signal. The memory device receives several bit-of address signals to identify the registration locations of the data in the memory device. Generally, speaking address signals are received by several address buffers. Each address buffer provides signal transition and buffering functions, and generates signals for decoding subsequent addresses. For response of any transition of any bit of the input address signal, ATD signal generation circuit always generates ATD signal. In addition to the address signals, other input signals may also trigger the ATD signal generation circuit to generate the ATD signal. These signals include chip enable signal and write enable signal. Both of them control the operation of the memory device.
Normally, before the address transition, the ATD signal has a logic 0 level. In order to respond to the address transition, the ATD signal generation circuit generates a logic-1 level pulse. The duration of the pulse, such as 10 ns, is determined by the timing unit of the ATD signal generation circuit. If the subsequent address transition occurs in the duration of the pulse, the pulse counting value is reset to maintain the integrity of the duration of the pulse.
In addition, the timing of some internal operations is performed by the timing response of the ATD signal. The internal operation comprises decoding the input addresses to select only one storage area for data read/write in the memory device. Beside, the ATD signal can serve as a synchronous signal.
Ideally, the duration of the ATD signal is equal to the worst decoding time of the whole memory device. Actually, due to the process and electrical property variation, the duration cannot be well controlled. In the conventional ATD signal generation circuit, a theoretically predetermined time is set, which is not adjustable. However, an improper duration of the ATD signal not only turns on the pumping circuit prematurely, but also affects the read/write speed of the memory device. In addition, it also turns on the sense amplifier of the data line prematurely, wasting some power unnecessarily.
In order to solve the problem described above, in the U.S. Pat. No. 6,169,423, voltages of word lines are used to adjust the duration of the ATD signal. The U.S. patent, however, has a disadvantage. Due to the limitation of the differential input terminal of the sense amplifier, the read speed for logic 0 level and logic 1 level are different. Accordingly, even if voltages of two word lines reach above the pre-set value, the two word lines do not necessarily have the same subsequent sensing speed for data. Moreover, the optimized duration of the ATD signal cannot be precisely obtained.